HW News: Samsung GDDR6, HBM3 R&D, PCI-e Gen4 Power, & Zen CCX Arch

In additional hardware news to what we published yesterday -- a look at Intel's Kaby Lake (7600K, 7700K, etc.), the X2 Empire unique enclosure, and Logitech's G Pro mouse -- we are today visiting topics of Samsung's GDDR6, SK Hynix's HBM3 R&D, PCIe Gen4 power budget, and Zen's CCX architecture.

The biggest news here is Samsung's GDDR6, due for 2018, but it's all important stuff. PCI-e Gen4 is looking at being fully ratified EOY 2016, HBM3 is in R&D, and Zen is imminent and finalized architecturally. We'll talk about it more specifically in our reviews.

Update: Tom's misreported on PCI-e power draw. The Gen4 PCIe interface will still be 75W.

Anyway, here's the news recap:

Transcript

Memory manufacturer Samsung is developing GDDR6 as a successor to Micron's brand new GDDR5X, presently only found in the GTX 1080 and Titan XP cards. GDDR6 may feel like a more meaningful successor to GDDR5, though, which has been in production use since 2008.

In its present, fully matured form, GDDR5 operates at 8Gbps maximally, including on the RX 480 and GTX 10 series GPUs. Micron demonstrated GDDR5X as capable of approaching 12-13Gbps with proper time to mature the architecture, but is presently shipping the memory in 10Gbps speeds for the nVidia devices.

Samsung indicates an operating range of approximately 14Gbps to 16Gbps on GDDR6 at 1.35V, coupled with lower voltages than even GDDR5X by using LP4X. Samsung indicates a power reduction upwards of 20% with post-LP4 memory technology.

Samsung is looking toward 2018 for production of GDDR6, giving GDDR5X some breathing room yet. As for HBM, SK Hynix is already looking toward HBM3, with HBM2 only presently available in the GP100 Accelerator cards. HBM3 will theoretically run a 4096-bit interface with upwards of 2TB/s throughput, at 512GB/s per stack. We'll talk about this tech more in the semi-distant future.

PCIe

Tom's Hardware this week reported on the new PCI Express 4.0 specification, primarily detailing a push toward a minimum spec of 300W power transfer through the slot, but could be upwards of 500W. Without even talking about the bandwidth promises – moving to nearly 2GB/s for a single lane – the increase of power budget will mean that the industry could begin a shift away from PCI-e cables. The power would obviously still come form the power supply, but would be delivered through pins in the PCI-e slots rather than through an extra cable.

This same setup is what allows cards like a 750 Ti to function only off the PCI-e slot, because the existing spec allows for 75W to push through the PCIe bus. PCI-e 4.0 should be ratified by the end of 2016 by the PCI-SIG team, but we don't yet know the roll-out plans for consumer platforms.

Zen

AMD also detailed more of its Zen CPU architecture, something we talked about last week when the company camped out near IDF for an unveil event. The Summit Ridge chips have primarily been on display thus far, showing an 8C/16T demo with AMD's implementation of SMT, but we haven't heard much about other processors.

AMD is ditching modules in favor of CPU Complexes, or a CCX, each of which will host four CPU cores. Each CCX runs 512KB of L2 Cache per core, as seen in this block diagram, with L3 sliced into four pieces for 8MB total low-order address interleave cache. AMD says that each core can communicate with all cache on the CCX, and promises the same latency for all accesses.

It looks like the lowest SKU chips will still be quad-cores at a minimum.

Host: Steve "Lelldorianx" Burke
Video: Andrew "ColossalCake" Coleman