The North Bridge, South Bridge, & Unified Chipset
Both AMD and Intel unified the old North Bridge and South Bridge into a single chipset. The North Bridge was previously responsible for communicating with PCI-e and memory, and the South Bridge communicated with SATA and IDE, USB, firmware chips, PCI, legacy devices, and audio. These days, all of these devices talk to either the CPU or the unified chipset. Also different in modern times, the memory controller has now been moved to the CPU, becoming an integrated memory controller for both AMD and Intel. Intel’s IMC and AMD’s SOC determine whether memory slots can operate in dual-channel or quad-channel, control memory clocks, manage DRAM refreshes, writing, and reading, and have some security features related to memory.
A modern chipset looks more like this Z370 block diagram from Intel. Intel connects its chipset to the CPU via an interconnect called “DMI,” or Direct Media Interface, which was most recently revised in 2015 to use four PCIe lanes connecting the CPU and Chipset. This can become a limiting factor in some extreme IO scenarios, like those where multiple NVMe RAID SSDs might exist in a system. DMI is capable of about 3.9GB/s throughput. If you look carefully at the diagram, you’ll notice that GPUs are able to bypass DMI and the chipset, as the CPU hosts its own PCIe lanes that are assignable to graphics devices. In this example, we have 16 total PCIe 3.0 lanes available.
We can next highlight the left side outputs from the Z370 chipset, connected via DMI. These are all for IO devices: In this scenario, we have 24 PCIe 3.0 lanes, 6 SATA 6Gbps ports, options for dozens of USB ports, an integrated MAC, and Gigabit Ethernet connected via an SMBus and PCIe x1.
All of these devices are known as High-Speed IO devices. For Intel chipsets, motherboard makers get a fixed number of HSIO lanes from Intel’s chipset, and those motherboard makers can then decide how to assign the lanes. For instance, some motherboard makers might prefer to allocate more lanes to SATA and fewer to USB, others might want to add more PCIe slots, and so forth.
As for graphics and PCIe off of the chipset, an Intel chipset is only capable of assigning 4x HSIO lanes to any single PCIe slot. Because SLI requires a minimum of x8, it is impossible to run an nVidia GPU off of the chipset in multi-GPU configurations. AMD cards can pull from the chipset, but they will be limited to x4 PCIe lanes, and will also be communicating through the DMI, rather than straight to the CPU.
Z370 comes with 30 HSIO lanes, with 24 that are assigned to PCIe, USB, and SATA. 14 lanes are assignable by the motherboard manufacturer. Note that Intel PCIe chipset lanes cannot be assigned to any device in greater quantity than a x4 configuration. A manufacturer can’t pull 8 chipset PCIe lanes to a PCIe slot, for instance.
Back to our diagram, Intel also uses SPI, or the Serial Peripheral Interface bus, to bridge the chipset and firmware, Trusted Platform Modules, and XTU. Whenever you flash BIOS with a new version, that’s communicated down SPI and into the physical firmware chip.
Finally, on the right side of the chipset, we see additional IO support for RAID and Intel Rapid Storage Technology, or RST.
You’ll notice that memory doesn’t directly communicate with the chipset. Instead, because modern CPUs use integrated memory controllers, or IMCs, the memory has a direct line to the CPU, just like the primary GPU does.
AMD’s modern Ryzen chipsets aren’t too different from Intel’s. The functionality and objective is the same, although the specific implementation is different.
AMD’s X370 chipset block diagram looks like this. We’ll highlight the blocks and interconnects as we go. The CPU still hosts its own PCIe 3.0 lanes for direct GPU communication, just like Intel’s configuration, but Ryzen has more PCIe lanes on the CPU. We have a total of 16 lanes for PCIe 3.0 graphics devices, 4 lanes for NVMe M.2 devices, and 4 lanes that the user can never directly use, because those communicate with the chipset. Like Intel, the CPU also has an integrated memory controller – or System on Chip, more appropriately for AMD – that allows a direct line to the memory. Desktop Ryzen supports dual-channel memory, whereas Threadripper supports quad-channel memory.
For the chipset, AMD allows some motherboard manufacturer flexibility, just like the Z370 chipset, by giving assignable lanes that can be switched around to other devices. If a motherboard maker is building a smaller board or wants to down-cost the board, they could also remove some devices – those lanes will just be left unused.
The chipset can support up to x8 PCIe 2.0, 6x SATA 6Gbps with RAID support, 2x USB 3.1 Gen2, 6x USB 3.1 Gen1, and 6x USB 2.0. Separately, note that all of AMD’s current Ryzen chipsets allow overclocking, whereas Intel’s overclocking is feature-locked to the Z-series and X-series.
We’ll leave you with the most common chipset differences and an explanation of naming schemes. Intel’s names include Q/B/H/Z and X chipsets. Without getting into all the details, Q and B were originally meant for business – though B has been assimilated by gaming boards – and H was meant as an affordable mainstream board. Z chipsets are the performance series, and primarily differ in unlocked overclocking support. X chipsets are incomparable to these and support the HEDT, or high-end desktop CPUs, like the 7980XE 18C CPU.
AMD’s chipset names primarily include A/B and X prefixes. AMD’s B-series and X-series chipsets are officially unlocked for overclocking, and primarily differ in price. B-series boards tend to be on the cheaper end of the spectrum.
As for the real differences, it primarily comes down to how many HSIO lanes each of these chipsets has. Intel segments additionally with overclocking limitations. Note that the chipset doesn’t dictate motherboard quality. VRM quality can be awful on a Z or X-series motherboard and could be better on a B- or H-series board. It’s entirely up to the motherboard manufacturer.
We’ll talk more about individual chipset-level differences in the future, but this should start you off.
Editorial: Steve Burke
Video: Andrew Coleman