What is a Chipset?

Click to enlarge. * = Modern CPUs include memory controllers on the CPU.

Simply put, a chipset is the central architecture that dictates compatibility for processor families and other modern technologies. At their very core, chipsets are a cluster of on-board devices and controllers that enable different configuration or compatibility options. With the help of seasoned programmer and soon-to-be calculator historian Jim Vincent, we were able to ascertain a solid, easy-to-follow analogy for chipsets.

The chipset is like a spinal cord that controls most of the devices responsible for communicating with the outside world; the CPU can be thought of as a disembodied brain -- it needs the chipset to be fully functional. All of the CPU's I/O goes through channels to the chipset, which then relays or receives information from other vital organs -- video cards, peripherals, disk drives, audio, USB, and so on.

In original PCs, everything used to hang off of one bus (including memory). These days, the computer consists of separated systems. The memory bus (DDR3 channels, of which there are normally more than one in modern systems), the bus to the bridge chips (chipset - northbridge/southrbidge, hypertransport or QPI) SATA buses, PCI-e (video cards), USB buses, legacy buses (PS2, RS-232, parallel ports) are all separate entities that communicate via lanes and channels, all feeding back into the CPU to help efficiently organize and manage instructions and interrupt requests.

In short, the chipset is an amalgamation of different motherboard technology and is interconnected for speedy communication between central devices. All these devices communicate with the CPU at one point or another during their regular transactions, but are filtered through various gatekeepers. This filtering helps the CPU in management of tasks, almost acting like translators or liaisons. All of this couples nicely with our "Where was your CPU born?" article, so if CPU fabrication is of interest to you, that'd be another great topic to learn about at the same time.

Enough theory! Let's take a look at an actual chipset! For purposes of simplicity, we'll start with Intel's X58 (LGA1366) chipset (left), which housed the first gen Nehalem i7 CPUs, and their newer Z68 chipset (right, click to enlarge both simultaneously).

What makes up a chipset?

Keep in mind that Intel and AMD often change naming between chipsets and generational architecture, but they are largely composed of similar devices:

Northbridge: Responsible for handling high-speed devices, like PCI-e video devices. In the X58 diagram (left side), this would be the IOH (input/output hub).

Southbridge: The southbridge, if it hasn't been merged into a PCH (platform controller hub, effectively a unified southbridge that's more powerful), deals with all low speed devices. These are normally audio, peripheral, or drive components. The X58 diagram uses the ICH10 (I/O Controller Hub) for a southbridge.

Memory Controller: The well-known Sandy/Ivy Bridge line (including SB-e) of Intel CPUs includes the memory controller on the CPU, but some older chipsets had a separate controller for this. The memory controller is part of what tells us whether a CPU/chipset can handle dual-, triple-, or quad-channel memory. The X58 allows triple-channel memory (note that it has three stemmed channels), while the Z68 is limited to dual-channel memory (two channels).

QPI: QuickPath Interconnect, Intel's competition to HyperTransport, acts as a highway between much of our chipset and the CPU. In the X58 chipset, we have a single QPI connecting the CPU to the IOH.

HyperTransport: While not displayed in either of our above diagrams, AMD's competing technology to Intel's QPI is called 'HyperTransport,' which, at its core, is a bidirectional bus like QPI. There are disparities between the two approaches to data transport, but the practical uses from a gaming perspective are similar.

In the end, the root composition of a chipset comes down to a coupling of the CPU, northbridge, and southbridge, which branch into high-speed and low-speed devices respectively. Memory and other I/O controllers and firmware also stem from these chips, although memory controllers tend to be integrated with CPUs in recent advancements.

More recent Intel CPUs have integrated the northbridge and southbridge into a single controller, called the PCH (platform controller hub), which is effectively a unified southbridge.

A chipset's multi-depth network starts with the northbridge and southbridge as the top "level," spidering out all other devices from them (although the southbridge is becoming increasingly obsolete) via lanes, channels, hubs, or QPI/HyperTransport technologies. The southbridge performs cleanup tasks and, as briefly mentioned earlier, handles low-speed devices (audio, drives, LAN, PCI-e x1, PCI, USB) -- it'd be fair to think of the southbridge as the "PR team" of the CPU -- while the northrbidge deals with VIPs, like higher-speed PCI-e devices. Communications bounce between the CPU, northbridge, and southbridge as devices managed by each controller are utilized, ensuring snappy response times.

The native caps for memory frequency are also defined in chipset diagrams -- again, referencing the Z68 image, we see that the Z68 natively supports 1333MHz memory. Overclocking (and motherboards that allow it) can increase this, of course.

Chipsets are limited to a set number of dedicated PCI-express graphics lanes (this is also based on CPU limits); in the X58, the first-gen, enthusiast-focused Nehalem CPUs were capable of supporting up to 36 lanes. This means that on an i7 Nehalem / X58 chipset, you could support two cards at PCI-e x16 (32 lanes) or four cards running on x8 (4x8 = 32 lanes). As most 2.X PCI-e devices don't use the full x16 bandwidth, the x8 restriction hasn't been much of a concern for performance.

Sandy Bridge (Z68) motherboards, on the other hand, dedicate 16 PCI-e lanes for GPU usage (which feed directly into the CPU) and another 8 lanes go to the southbridge. If you were to connect two full-size discrete video devices to PCI-e slots on a board with the NF200 chip, the primary PCI-e x16 device (PCIe x16_1) would drop to x8, allotting it only 8 lanes for direct communication to the CPU. Running in x8/x8 is not typically detrimental with the previous generation (GTX 5x, RADEON 6x) GPUs, and generally only sees a 1-3% performance dip.

Including all the above items we've covered, modern chipsets have made new additions to their family of technologies that are supported by CPUs, bridges, and corresponding firmware: UEFI BIOS (Unified Extensible Firmware Interface Basic Input/Output System) has been a major recent inclusion to motherboards, enabling mouse functionality and shiny graphics; integrated graphics, of course, are frequently discussed when the Sandy Bridge overhaul is brought up (however weak they are), which the Z68 enables; SSD caching is another such addition, which allows smaller SSDs to act as a sort-of buffer, with the intent of diminishing the biggest bottleneck in any system (that'd be the drives); better overclocking functionality is yet another formidable Z68 upgrade. Differences between all the chipsets isn't really within the focus of this article, though, so we won't go into much depth with all that.

Hopefully all of this gives a nice, easy-to-follow top-level understanding of how chipsets work and what, exactly, they're good for (everything!). If you have any questions at all, or if you think we've missed something, comment below and let us know what's up. I'd be happy to answer anything I can or make updates as questions are asked. As always, our hardware forums are available for more in-depth discussions.

-Steve "Lelldorianx" Burke

Big thanks to Jim Vincent, calculator collector extraordinaire, for his explanations and analogies.