In the meantime, we've got news on the SF3700 controllers.
We've already discussed the importance of this next generation's controller architecture for SSDs. The industry is moving away from the SATA III (6Gbps) interface as SSDs gain traction in the consumer market; SATA Express (at 10Gbps) and PCI-e 2.x x4 (at 16Gb/s) are more desirable options, but existing consumer controller architecture doesn't adequately make use of available bandwidth.
PCI-e is significantly advantaged over the SATA interface for many reasons, but one of the most important differentiating factors is its bi-directional bus. PCI-e is capable of simultaneously transferring data both ways on the interface, meaning that connected devices can send and receive data (I/O -- reads and writes -- in this case) without needing to delay between each operation. Up through now, PCI-e SSDs have struggled to achieve throughputs higher than 1200MB/s (100% read), even though a theoretical maximum would plant performance around 1800MB/s on an x4 configuration (PCI-e 2.1 x4 transfers at 2GB/s). It is our understanding that this limitation is likely an artifact of how the drive cache is handled on existing PCI-e consumer solutions -- namely that they use all cache for R/W operations / metadata instead of splitting the cache more evenly, which makes for more difficult swapping and garbage collection.
SandForce claimed at Flash Memory Summit today that they've managed to utilize the full x4 bandwidth available from the interface, maxing-out the impending SF3700 controller at 1800MB/s 100% sequential read operations in design. The company overlaid its own SF3700 datarate on top of a benchmark performed by TweakTown, generating the following slide:
Shown here, SandForce claims that its 80/20 (R/W percentage) sequential performance lands its device well above competing SATA and PCI-e / mSATA devices, resting at 1400MB/s transfer. SandForce emphasized that most SSDs presently generate a "bathtub curve" on performance charts, meaning that they tend to perform best toward 100% read and 100% write, with poor performance between. Alleging an unrealistic use case scenario, the company then went on to highlight its higher target performance in more real-world mixed workload (R/W) environments.
SHIELD Error Correction & Drive Endurance
Again, SHIELD is something we previously explained in the initial SF3700 write-up. The new data from SandForce suggests that its error correction technology is capable of significantly amplifying NAND endurance by modifying its error correction code rate (historically 55 bits per 512-byte sector on MLC). The end result is that 3K P/E (program/erase -- the amount of times the NAND can be written and erased before death) can conservatively be boosted to 5K P/E cycles strictly by using smarter error correction on the controller side. The effect scales to a theoretical maximum of 15x the P/E cycles by using stronger codes, which would result in 45K P/E cycles on 3K NAND. This is more of an outlier, really, but even at 5K P/E cycles from 3K, that's a major endurance gain for consumer and enterprise devices.
As for what manufacturers will be using SandForce's Gen3 controller, we can't yet say, but it'd be safe to state that "existing manufacturers have no reason not to update product lines." Ahem.
We'll have more on controller architecture in a future analytical piece. Stay tuned to the site for that information.
- Steve "Lelldorianx" Burke.