In this shift, AMD points-out Polaris as achieving 2.5 times the performance per Watt as seen on the 28nm GPUs released in 2H15-1H16. We previously looked at initial Polaris samples at CES, where the company was running a black box demo of a GTX 950 vs. Polaris; see that here. This “Polaris” marking on the roadmap is indicative of the immediate future for AMD's GPUs but, looking further outward, we learned that AMD's explicit inclusion of HBM version 2 will begin with Vega. The suggestion, then, is that HBMv2 should begin shipping through AMD by 2H17 (and that Polaris probably won't be outfitted with HBMv2). Further out is Navi, which hopes to introduce “scalability” and “Nextgen memory” – whatever's after HBMv2. Link's favorite high-pitched helper will be due around 2018, based upon the initial roadmap.
(Above: Our interview with AMD's Roy Taylor, discussing VR, Dx12, & driver support).
Just from looking at the roadmap, it would appear that Vega can expect around a 1.5-2x gain in perf/Watt over Polaris, and that Navi is somewhere around the same realm of gains (if slightly higher). Bear in mind that this is looking far enough into the future that everything could change.
HBM2 is known to be in nVidia's high-end Pascal architecture GPUs, slated for arrival sometime this year. Low-end versions (GP104) of Pascal will be equipped with GDDR5X memory from Micron. This brand new memory type pushes between 10 and 14Gbps of data, a surge over the ~8Gbps of GDDR5 “non-X” memory. The rest of Pascal will be HBM2-equipped. That puts AMD as competing directly against Pascal in the memory department by EOY 2017. AMD and its absorbed ATi have traditionally been first-to-market with new memory technologies, including several types of GDDR memory and the first iteration of HBM. NVidia might be able to take one of those “first-to-market” tallies from AMD with HBM2 on Pascal, depending on Vega's shipping date.
In the meantime, here's the need-to-know information:
Samsung fabs HBM2 memory, and has already begun mass roll-out of the dies. The first iteration of HBM has a memory interface size of 1024-bits wide (128 bits per stack) and offered a bandwidth of >100GB/s per stack, compared to GDDR5's 32-bit stack width and 28GB/s per-chip memory bandwidth. HBM2 will double throughput of HBM by moving to 8 dies per staple. Speaking to predictions outside of GPUs, GN staff expects to see CPUs eventually adopt HBM to begin a slow process of shifting memory away from the motherboard and onto the physical CPU die.
Check back for at least one more video interview and article from our time with AMD. Plenty of game news to come later today, too.
- Steve “Lelldorianx” Burke.