Ask GN: VCCIO & PLL, Make-or-Break Architectures, & FRAPS ReplacementWednesday, 27 April 2016
The first “Ask GN” since leaving for PAX East, we delve into topics exploring voltage configurations for overclocking, AMD's Zen / Polaris architectures and the make-or-break pressure, alternatives to FRAPS in DirectX 12/Vulkan, and upgrades.
The questions are posted below the video with timestamps, as always.
For anyone interested in the final question in the video (paraphrased: “Should I buy Polaris or Pascal and sell my 980 Ti?”), you may be interested in our recent “Polaris & Pascal: Buy or Wait?” content we published.
Major CPU Thread Optimizations in Total War: Warhammer - Detailed LookSaturday, 23 April 2016
We spoke exclusively with the Creative Assembly team about its game engine optimization for the upcoming Total War: Warhammer. Major moves to optimize and refactor the game engine include DirectX 12 integration, better CPU thread management (decoupling the logic and render threads), and GPU-assigned processing to lighten the CPU load.
The interview with Al Bickham, Studio Communications Manager at Creative Assembly, can be found in its entirety below. We hope to soon visit the topic of DirectX 12 support within the Total War: Warhammer engine.
Ask GN: Hopes for AMD Zen, Limited CPU Gains, & Future of MonitorsSaturday, 16 April 2016
This fifteenth episode of Ask GN springs forth a few quick-hitter questions, but a couple that require greater depth than was addressable in our episodic format. These longer questions will be explored in more depth in future content pieces.
For today, we're looking at the future of AMD's Zen for the company, forecasting HDR and monitor tech, discussing IGP and CPU performance gains, and talking thermals in laptops. As always, one bonus question at the end.
Timestamps are below the embedded video.
Mercury Memory, Vacuum Tubes, & First Transistors - Computer History Museum TourThursday, 14 April 2016
5MB of storage once required 50 spinning platters and a dedicated computer, demanding a 16 square-foot area for its residence. The first hard drive wasn't particularly fast at 1200RPM and with seek latencies through the roof (imagine a header seeking between 50 platters) – but it was the most advanced storage of the time.
That device was the IBM 305 RAMAC, its converted cost was a $30,000 monthly lease, and single instruction execution required between 30ms and 50ms (IRW phases). The IBM 305 RAMAC did roughly 100,000 bits per second, or 0.0125MB/s. Today, the average 128GB microSD card costs ~$50 – one time – and executes read/write instructions at 671,000,000 bits per second, or 80MB/s. And this is one of our slowest forms of Flash storage. The microSD card is roughly the size of a fingernail (32x24x2.1mm), and filling a 16 square-foot area with them would yield terabytes upon terabytes of storage.
The 305 RAMAC was a creation of 1956. Following last week's GTC conference, we had the opportunity to see the RAMAC and other early computing creations at the Computer History Museum in Mountain View, California. The museum encompasses most of computing history, including the abacus, early Texas Instruments advanced calculators (like the TI-99), and previously housed a mechanical Babbage Machine computer from the 1800s. In our recent tour of the Computer History Museum, we focused on the predecessors to modern computing – the first hard drive, first supercomputers, first transistorized computers, mercury and core memory, and vacuum tube computing.
NVIDIA Pascal P100 GPU Enters Volume Production, Ships “Soon”Tuesday, 05 April 2016
Pascal is the imminent GPU architecture from nVidia, poised to compete (briefly) with AMD's Polaris, which will later turn into AMD Vega and Navi. Pascal will shift nVidia onto the new memory technologies introduced on AMD's Fury X, but with the updated HBM2 architecture (High Bandwidth Memory architecture version 2); Intel is expected to debut HBM2 on its Xeon Phi HPC CPUs later this year. View previous GTC coverage of Mars 2030 here.
HBM2 operates on a 4096-bit memory bus with a maximum theoretical throughput of 1TB/s. HBM version 1, for reference, operated at 128GB/s per stack on a 1024-bit wide memory bus. On the Fury X – again, for reference – this calculated-out to approximately 512GB/s. HBM2 will double the theoretical memory bandwidth of HBM1.
AMD to Ship HBM2 GPUs by End of Year with VegaTuesday, 15 March 2016
AMD's GPU architecture roadmap from its Capsaicin event revealed the new “Vega” and “Navi” architectures, which have effectively moved the company to a stellar naming system. A reasonable move away from things associated with hot, at least – Volcanic Islands, Hawaii, and Capsaicin included.
Pascal GP104 Architecture Unsurprisingly Deploying GDDR5X at Low-EndSaturday, 12 March 2016
This isn't news to anyone who's followed the site through our Pascal and GDDR5X posts, but new leaks by “benchlife.info” indicate nVidia's dedication to use both HBM and GDDR5X. The Chinese language site has previously proven to be reliable in its leaks.
GPU architecture has come to a head with memory. Pascal will host HBM2 on its high-end devices, but the cost makes low-end and mid-range cards (the equivalent of a current GTX 960) impossibly expensive. NVidia plans to deploy Micron's new GDDR5X high-bit-rate memory for a cheaper alternative to HBM2; GDDR5X is more expensive than GDDR5, landing it between the oldest (current) and newest (current) technology in product cost.
Week's HW News: 10nm Intel Chips, Record nVidia Revenue, & AMD News
Last week primarily featured initial Vulkan benchmarks – a stepping stone toward full integration of the new API within games – and major silicon manufacturer news. Intel declared plans to ship 10nm chips by 2H17, nVidia boasted record revenue of $1.4B for its fiscal quarter, and AMD pushed improved Linux drivers to the public. The Intel push is the most interesting, with the company definitively indicating that it will not delay 10nm chip manufacturing past 2017. As the silicon manufacturers near the lower limit of current technology and processes, each of these iterative jaunts toward (what we'd expect to be) something like 1nm carbon nanotubes gets increasingly difficult. Seeing single-digit percentage point increases in overall performance (gaming, production) isn't quite as impressive as the reduction in power and significantly increased transistor count.
Learn about each of these items in more depth here:
AMD Hands-On: Polaris Demo vs. GTX 950, Future of HDR Screen TechnologyThursday, 07 January 2016
AMD’s new Polaris architecture discretely sat in the company’s CES 2016 suite, running Star Wars Battlefront with impressively low system power consumption. Quietly the GPU sat, running a completely new architecture and process for GPUs. No fanfare, no bombastic marketing videos projected on the walls, no product unveil insanity.
The demo was simple: Show two Intel i5 Haswell systems side-by-side, one with an nVidia GTX 950 ($160) and one with AMD’s undisclosed Polaris GPU. AMD locked framerate to 60FPS in the demo, showing both GPUs at a constant 60FPS using the X-Wing Survival map (singleplayer), and directing focus toward Kill-A-Watt wall meters. The wall meters show total system watt consumption and, as one would expect from an AMD suite, the AMD-powered system ran at lower total system power consumption overall.
Chris Roberts on Star Citizen Engine Architecture & Zoning OptimizationFriday, 02 October 2015
Our most recent interview with Cloud Imperium Games' Chris Roberts became a two-parter, following an initial discussion on DirectX 12 and Vulkan APIs. Part two dives deeper into the render pipeline, network and render optimization, zoning, data organization, and other low-level topics relating to Star Citizen. A lot of that content strays from direct Star Citizen discussion, but covers the underlying framework and “behind-the-scenes” development operations.
Previous encounters with Roberts have seen us discussing the game's zoning & instancing plans in great depth; since then, the Roberts has brought-up the system numerous times, expressing similar excitement each time. It is clear to us that the zoning and instancing architecture have required a clever approach to problem solving, evidenced to us by a previous pre-interview conversation with the CIG CEO. In a pre-shoot talk, Roberts told us that he “loves engineering problems,” and had considered the instancing system to be one of the larger engineering challenges facing Star Citizen. The topic of instancing was again revisited in this sit-down, though at a lower, more technical level.
We moderate comments on a ~24~48 hour cycle. There will be some delay after submitting a comment.