Where did Z97 come from?
Z97 was not the premiere platform that shipped with Haswell, which is the architecture found on Haswell, Haswell Refresh, and Devil's Canyon. The initial platform used Z87, but was refreshed for the shipment of Intel's faster-clocked Devil's Canyon processors.
Z97 vs. Z87 changed a few things, primarily in the realm of storage technology. Z97 introduced SATA Express and M.2 support to the platform, permitting on-chipset PCI-e Gen2 lanes to be allocated to SSDs that utilize the PCI-e interface. Z97 served as a means to ready the market for migration to Z170, adapting for modern storage technologies in the interim between CPU architectures.
That's the only reason Z97 came to exist.
Z170 Chipset Specs & Changes
Z170 introduces a number of changes to platform architecture. View the above diagram for an initial look.
The Desktop Management Interface (DMI) that bridges communications between the CPU and chipset has been updated to version 3.0, entering territory of PCI-e 3.x transfer rates. This shift has increased the data sample rate from 5GT/s (gigatransfers, of which 1GT = roughly one billion transfers per second) to 8GT/s. The increase results in nearly a 2x sample rate jaunt, the equivalent of moving from 2GB/s to 3.93GB/s.
This is the lowest-level we'll go for sake of GamersNexus and covers the critical CPU-to-chipset pipe.
Moving on to more familiar items, some of the easy changes include support for ten total USB3.x ports (from six), USB3.1 Gen2 support, and Intel “Smart Sound.” Smart Sound integrates support for voice commands (wake on voice) and audio FX (virtual surround, DTS) natively on the CPU.
Beyond these relatively minor details, the Z170 chipset has added to the PCI-e lane availability over Z97, but does so with a few caveats. On paper and in the above block diagram, Z170 boasts 20 PCI-e 3.0 lanes – a marked gain over Z97's 8 PCI-e 2.0 lanes – but the graphic doesn't specify restrictions. Keep in mind that PCI-e lanes can be allocated to much more than graphics, primarily SSDs that communicate using the PCI-e interface (M.2, for instance), and Intel accounts for this. The chipset divides its 20 PCI-e lanes into clusters of four, so that's five sets of four PCI-e lanes. Three of the PCI-e lanes are allocated to Intel's Rapid Storage Technology (RST), enabling RAID SATA-e configurations. Note well that because of the division of lanes, the maximum supported single-card from-chipset allocation is x4, meaning that tri-SLI will not be supported natively given nVidia's hard x8 minimum requirement. CrossFire will allow for x4 lane assignment. In order to assign more lanes to an expansion graphics card, motherboard manufacturers will have to resort to multiplexing chips (PLX/PEX chips) as they've done in the past.
The primary gain from the huge count of PCI-e lanes is going to be in storage applications. Intel's Z170 chipset has 26 total high-speed IO (HSIO) lanes available, and allows the board to divide them between controllers with relative freedom. That allows for greater customization on the side of motherboard manufacturers and, hopefully, some deviation from market norms.
Separately, Intel has made revisions to its accompanying Gigabit ethernet controller, hopefully readying-up for the incoming adoption of fiber across various municipalities. Most of these changes mitigate power consumption and improve power efficiency, advantages that will primarily be observed at the enterprise and biz-client levels.
Intel's other Skylake-class chipsets are not yet available, but will retain traditional branding. Thus far, we know that H170, H110, and B150 exist, alongside Q150. H170 will likely be a chipset with fewer overclocking and enthusiast provisions, making for cheaper motherboards in use cases where neither item is demanded.
More to come as we continue to learn about Skylake.
- Steve “Lelldorianx” Burke.