HW News - NVIDIA RTX 3080 12-pin Cable Detailed, DDR5 Spec Finalized, Intel i9-10850K

By Eric Hamilton & John Tobin Published July 20, 2020 at 11:00 pm
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While the week started off rather slowly, hardware news picked up towards the end of the week. As such, we have plenty to cover, including a GN exclusive, in which we’re able to confirm the rumored 12-pin PSU connectors for Nvidia’s Ampere. The father of Linux, Linus Torvalds, is also back in the news, this time with a rant over AVX-512. We also go over the finalized DDR5 spec, which will set the stage for industry adoption in 2021. 

Elsewhere, we have a bit more news on Apple Silicon as it relates to manufacturing, a fresh Alder Lake rumor, Skylake-X Refresh reaching EOL, and a bit more. As always, the news article and video embed follow below.

01:01 | Charity Auction for the NZXT BLD

After our critical review of NZXT’s BLD series, we decided we don’t want the system anymore. We’re making it available via charity auction, with 100% of the sale benefiting Cat Angels Pet Adoptions (which we have personally visited and with whom we’ve worked in the past). If you’d like to check out the auction, check this link.

02:46 | 3900XT Extreme Overclocking Stream Recap

Exclusive to the video embed. It’s just a quick recap of our latest liquid nitrogen livestream.

04:51 | Confirmed: 12-Pin Connectors For Ampere, Likely OEM Focus

This week, there’s been a rumor making the rounds that 12-pin connections from the PSU are in order for new Ampere cards. GN has independently confirmed that this is true: 12-pin connections for Ampere are legitimate. Though, as we currently understand it, it isn’t likely to have an effect on the current DIY/enthusiast space. To make it clear, it’s highly unlikely you’ll need a new PSU for Ampere, at least not for lack of proper cables, anyway. 

12-pin connectors have been in discussion at Nvidia for a few years now, and GN has even reaffirmed this with  now-former Nvidia employees. We’ve also talked to all the major AIB partners and have been able to confirm that custom cards, and even custom coolers based on the reference PCB, will ship with 2x 8-pin or 3x 8-pin connectors, (the latter being aimed at serious overclockers) rather than a single 12-pin connector. 

A single 12-pin connector is capable of delivering 600W, versus 2x 6-pins at 225W (150W + 75W from PCIe x16 slot) or 2x 8-pins at 375W (300W + 75W from PCIe x16 slot).  

Rather, as we understand it, Nvidia’s reference (FE) cards will have a 12-pin connector, and may even come with an adapter -- something like an adapter from 2x 8 to 1x 12-pin connector. However, we’re not sure if these cards will make it to the retail channel, or if they will be strictly an OEM focus. We’re leaning towards the latter. Furthermore, it’s likely that OEMs like HP and Dell, and maybe even system integrators will be the primary customer for 12-pin cards.

We also know, based on a cable factory we toured about a month ago, that manufacturers are scrambling to get the tooling and molds ready for 12-pin cables. What we aren’t entirely sure of is just how widespread 12-pin connector cards will be.   

Source: GN

09:10 | Linus Torvalds Calls AVX-512 A “Power Virus”

Linus Torvalds, the resident curmudgeon of the tech community, is back with another hot take. This time, it has to do with Alder Lake possibly not supporting the AVX-512 instruction set (more on that in a bit). And, as is usually the case with Mr. Torvalds, he doesn’t mince his words about his loathing for AVX-512.

“I hope AVX512 dies a painful death, and that Intel starts fixing real problems instead of trying to create magic instructions to then create benchmarks that they can look good on. I hope Intel gets back to basics: gets their process working again, and concentrate more on regular code that isn't HPC or some other pointless special case,” said Torvalds via a mailing list (via Phoronix). 

Torvalds didn’t stop there, going on to say that “AVX512 has real downsides. I'd much rather see that transistor budget used on other things that are much more relevant. Even if it's still FP math (in the GPU, rather than AVX512). Or just give me more cores (with good single-thread performance, but without the garbage like AVX512) like AMD did.”

The rant continued, with Torvalds going as far as to say “I want my power limits to be reached with regular integer code, not with some AVX512 power virus that takes away top frequency (because people ended up using it for memcpy!) and takes away cores (because those useless garbage units take up space).” Ouch.

AVX-512 is a wider vector-based instruction set that Intel has been using since at least 2013, and despite Torvalds’ self-admittedly “biased” and “grumpy” rant, it likely isn’t going anywhere. 

Source: 

https://www.phoronix.com/scan.php?page=news_item&px=Linus-Torvalds-On-AVX-512

11:40 | JEDEC Finalizes DDR5 Spec

Over the last few months, we’ve mentioned the looming DDR5 spec on the horizon. Now, JEDEC has finalized the spec, publishing it as the JESD79-5 DDR5 SDRAM standard. Frankly, there’s a lot to go through, and it won’t all be within the scope of this content. However, we’re going to list the highlights and biggest takeaways. We may devote more time to DDR5 in a separate piece in the future. 

One of the biggest changes for DDR5 is the doubled burst length to BL16, and doubling the  bank count to 32. These are both numbers we’ve mentioned before, when SK Hynix detailed some of its early DDR5 specs. The idea here is to increase memory access availability and allow for better memory scaling at higher frequencies, without compromising channel efficiency. As with previous DDR evolutions, DDR5 will double data rates and offer a significant uplift in density. 

  • DRR5 will support double the bandwidth of DDR4, starting at 4.8 Gbps, which is roughly a ~50% increase over the end-of-life speed of 3.2 Gbps for DDR4. 
  • DDR5 will support a “max” data rate of 6.4 Gbps; however, as with current DDR4, that’s likely to be exceeded; SK Hynix has plans for DDR5-8400. 
  • DDR5 will offer single memory chips up to 64Gbits in density, well beyond DDR4’s 16Gbit maximum. DDR5 also supports die stacking, allowing 8 dies to be stacked as a single chip. 
  • UDIMMs will support up to 128GB
  • DDR5 will now offer two 40-bit fully independent channels on the DIMM. Burst Length per channel is going from BL8 to BL16.
  • DDR5 will introduce a “Fine grain refresh feature.” We touched on this previously when SK Hynix discussed its “Same Bank Refresh,” which allows the CPU to access certain memory banks while others are in operation or refreshing. Same idea here, with the end goal being improving latency and memory bank access. 
  • DDR5 will operate at 1.1V, down from 1.2V for DDR4. DDR5 will also employ an on-DIMM voltage regulator. This means that motherboards supporting DDR5 won’t need to regulate DIMM voltage. This likely has implications for the cost/complexity of the DIMMs.  
  • DDR5 will have an on-die ECC
  • DDR5 maintains the same 288-pin count as DRR4, but pinout has changed.

Industry adoption is set to begin in 2021. As usual with new standards, the server market will see the first commercial adoption, with client and consumer applications coming afterwards.    

https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond

Presentation slide deck: https://www.anandtech.com/Gallery/Album/7660

15:36 | Rumor: Alder Lake’s Hybrid Computing Can’t Use AVX-512 Or FP16

More and more, it seems that the theory we’ve previously mentioned, the one where Alder Lake will see Intel mix both big and little cores, could be a reality. In a new leak by Twitter user @9950pro, a technical document from Intel shows no less than three ADL SKUs with different configurations. 

The products mentioned, with no official SKUs attached to them, appear to show different big/little core arrangements and TDPs. Of the CPUs listed, all are designated as Alder Lake-S, and two of them show an 8+8+1 listing; the other CPU shows a 6+0+1 listing. According to the document, these numbers illustrate 8 big cores, 8 small cores, and “GT1”. In the case of the 6+0+1, that apparently means 6 big cores, 0 smaller cores, and “GT1”. 

The document states that the big and small cores share the same instruction set and model specific registers, and that when hybrid computing is enabled, the available instruction sets are limited. This appears to hint at the possibility that when using a mixture of both big and small cores, AVX-512 and FP16 won’t be enabled. Rather, those two instruction sets only seem to be available when strictly using just the big cores.   

Source: https://twitter.com/9550pro/status/1282699708855496705

17:09 | Intel Core i9-10850K Listing on Pre-Built Sites

Earlier this year, with the release of Intel’s Comet Lake S series of processors, we saw what seemed to be the full extent to which Intel’s 14nm process could be pushed with the flagship Core i9-10900K boosting well beyond 5 GHz across its 10 cores, but that kind of binning could be hard to maintain. We’ve seen the result of this in the form of a shortage of the 10900K across multiple marketplaces lasting from the time of release a couple of months ago through today. Now, Intel seems to be trying to alleviate this shortage by releasing a new Core i9 series processor.

Intel, apparently not wanting to let any numbers or letters go unscathed, is reportedly calling this new processor the Core i9-10850K, and it appears to essentially be a 10900K but 100MHz slower in both base and boost clocks making the base clock 3.6GHz and the boost clock 5.2GHz while retaining all 10 cores and 20 threads of the 10900K. These processors were likely destined to be 10900Ks, but they just didn’t quite make the cut, so now they’re labeled as 10850Ks and sold for cheaper. 

This processor first appeared in benchmarks early this month, but has now been more solidly confirmed as it has been spotted in a Digital Storm system configuration by Twitter user @momomo_us. According to the Digital Storm listing, the 10850K will be $73 more expensive than the 10700k placing the 10850K in the $450 price range, which is $50-$100 less than the 10900K sells for when it’s available.

At this point, it’s unclear whether the 10850K will be exclusive to pre-built systems or if it will also be available separately, but the existence of this processor is likely to alleviate the difficulties of such strict binning of the 10900K, potentially allowing the 10900K to last on shelves longer with the lower cost 10850K alongside it.

[reverse XT comment]

Sources: https://www.techradar.com/news/intel-core-i9-10850k-shows-up-online-and-could-cause-some-core-i9-10900k-buyers-remorse

https://wccftech.com/intel-core-i9-10850k-10-core-desktop-cpu-specs-price-leak/

https://twitter.com/momomo_us/status/1283735054389141504 

Original leak: https://twitter.com/TUM_APISAK/status/1279016593926701056

20:38 | Skylake-X Reaches EOL

Another week, another wave of PCNs to parse through. This week, it seems Intel’s Skylake-X is set to be retired. For those keeping track, this is technically 9th-gen silicon, and is actually Skylake-X Refresh. Skylake-X Refresh was already supplanted by Cascade Lake-X some time ago, and Intel even historically lowered prices on its HEDT lines in light of AMD’s aggressive Threadripper offerings.

The SKUs set to make their exit are as follows: i7-9900X, i9-9820X, i9-9900X, i9-9920X, i9-9940X, i9-9960X, i9-9980XE, and the i9-9990XE. All Skylake-X Refresh SKUs were based on the Basin Falls Refresh platform, used the LGA 2066 socket, and required X299 chipset-based motherboards.

Along with Skylake-X Refresh, Intel is also sunsetting most of the Skylake-W Xeons, which makes sense, as these have also been succeeded by Cascade Lake-W. Should you decide you can’t live without a Skylake-X Refresh chip, you’ve got until January 22, 2021. After that, Intel will ship final orders on July 9, 2021. 

Source: https://qdms.intel.com/Portal/SearchPCNDataBase.aspx

PCN #: 117671-00

22:00 | New AMD Radeon Raise The Game Bundle

AMD just announced a new Radeon “Raise the Game” bundle with select Radeon graphics cards. The first of these bundles includes the game “Godfall” with the purchase of an RX 5500 series graphics card - that would include the RX 5500, 5500 XT as well as eligible 5500 powered laptops. AMD is also offering a bundle of “Godfall” and “World of Warcraft: Shadowlands” with the purchase of 5600 and 5700 series GPUs both on mobile and desktop platforms. This offer runs from July 14th, 2020 through October 3rd, 2020 and the bundled titles will be able to be redeemed from the time of the release of the games through November 7th, 2020.

Source: AMD

22:56 | Apple Looks To TSMC To Build Apple Silicon

Unsurprisingly, early reports out of Digitimes are suggesting that TSMC is on tap to manufacture Apple’s new Arm-based silicon destined to replace x86 Intel CPUs in Macs. Apple is already a top TSMC customer thanks to its A-series SoCs, and being that Apple will want its Apple Silicon on the most advanced node possible, TSMC is probably the best choice.

The report, which is paywalled, also suggests that TSMC is expecting to ramp production for Apple silicon in the first half of 2021, as Apple has reserved capacity. Per 9to5Mac, TSMC is expecting Apple’s orders to account for a large portion of its wafer sales in the first half of 2021. 

“TSMC to see orders increase for Arm-based Macs in 2H21: TSMC is expected to see orders for Apple’s Macs based on its Arm-based silicon ramp up and contribute substantially to the foundry’s wafer sales starting the second half of 2021, according to industry sources,” says Digitimes (via 9to5Mac). 

Apple is set to introduce its first Arm-based machine this year, widely believed to be a smaller MacBook or Macbook Air. However, we may very well see a proper Mac Pro by the end of 2021 with Arm-based silicon in it.  

Source: https://www.digitimes.com/news/a20200716PD204.html

24:30 | New Products: Razer Tiny Keyboard, Corsair “NEXUS” Screen

Corsair Nexus:

Corsair has launched the Corsair iCUE NEXUS touch screen, which Corsair purports to be a “companion touch screen” that can serve a variety of functions. This seems to be similar to their elgato stream deck line of products but with less of a focus on macro functionality and more of a focus on system monitoring and iCUE management. The Nexus has a 5 inch diagonal screen with a resolution of 640 x 48 pixels. Up to 256 different screens can be saved and swapped between with up to 6 buttons on each screen that can be programmed to change iCUE settings such as lighting, fan control, mouse DPI etc. The buttons can also be set to custom macro controls or to launch applications. Additionally screens can be used to display system performance and temperature information through iCUE. According to Corsair, this iCUE functionality can be used even without launching the iCUE client, which might be enticing to some users. The Corsair Nexus is available now on Corsair’s website for $100.

Source: https://www.corsair.com/us/en/Categories/Products/Accessories-%7C-Parts/CORSAIR-iCUE-NEXUS/p/CH-9910010-NA

Razer Huntsman Mini:

Razer has released a new keyboard in the Huntsman line in the form of the Razer Huntsman Mini. The Huntsman Mini is a 60% mechanical keyboard, which in case you’re not familiar is the smallest common keyboard form factor. The Huntsman mini has RGB backlighting that can be controlled either with Razer Synapse or with a series of preloaded lighting effects that can be cycled through without Synapse running. Since the 60% form factor requires compromises in terms of the number of keys on the keyboard, many of the keys on the Huntsman Mini have secondary functions that are printed on the sides of the key caps facing the user and can be used with the function key. The Huntsman Mini is available in both black and mercury white with Razer’s red and purple optical mechanical key switches, and is on sale on Razer’s website now starting at $120 with the purple switches and $130 with the red switches.

Source: https://www.razer.com/gaming-keyboards/razer-huntsman-mini/RZ03-03390100-R3M1

Editorial: Eric Hamilton, John Tobin
Additional Reporting, Host: Steve Burke
Video: Keegan Gallick, Andrew Coleman

Last modified on July 20, 2020 at 11:00 pm

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